1. Field of the Invention
The present invention relates to a digital television receiver and more particularly to a timing recovery device in a digital television receiver using a vestigial side band (VSB) system.
2. Discussion of Related Art
As the next generation of digital TV system, the High Definition Television (HDTV) has been continually developing to ultimately bring the theater right into the living room of a viewer. When compared with an existing analog TV, a digital TV not only has a higher resolution and a larger size in the horizontal direction, but produces a vivid sound comparable to a compact disc via a multi-channel. However, due to the many ways to transmit the data, a standardization of the digital TV (DTV) is still being settled among companies mainly in U.S.A, Europe and Japan.
In U.S.A., a VSB system proposed by Zenith has been adapted as a transmission format, a Motion Picture Expert Group (MPEG) has been adapted as a video compression format, a Dolby AC-3 has been adapted as an audio compression format, and an existing but compatible display method has been adapted as a display format. To transmit compressed image data under the above standards for a DTV, an error correction coding (ECC) is executed on the compressed image data. Particularly, a synchronizing signal is inserted between data at predetermined periods before transmission, thereby facilitating the recovery of the data at a receiving side.
The synchronizing signal is classified into two kinds, where one is a horizontal synchronizing (hsync) signal commonly called xe2x80x98a data segment synchronizing signalxe2x80x99, and the other is a vertical synchronizing (vsync) signal commonly called xe2x80x98a field synchronizing signalxe2x80x99. The hsync and vsync signals of the digital TV differ from the horizontal and vertical synchronizing signals of a National Television System Committee (NTSC) television.
FIG. 1 shows a transmission signal frame of the digital TV in a VSB system. As shown, one frame is comprised of two fields, where each field includes 313 data segments and where each data segment includes 832 symbols of 4 hsync signals and 828 data symbols. Because the hsync signal does not undergo the ECC process, each data segment includes 4 symbols of hsync signal and 828 symbols of ECC signal. Also, one of the 313 data segments in each field is a vsync segment containing a training sequence and the remaining 312 are general data segments.
Also, before transmission from a transmitting side such as a broadcasting station, the signal to be transmitted is passed through a mapper by which the signal is changed into desired power levels. For a terrestrial broadcasting type of 8 VSB, the output level of the mapper corresponds to one of 8-step symbol values (amplitude level) xe2x88x927, xe2x88x925, xe2x88x923, xe2x88x921, 1, 3, 5, 7. Moreover, according to a predetermined agreement, the mapper forcibly inserts the 4 symbols of the hsync signal for every 832 symbols and forcibly inserts the vsync signal in the position of every 313th data segments.
Furthermore, with two logic levels, a prescribed logic level of the hsync signal xe2x80x981, 0, 0, 1xe2x80x99 is continually repeated in every data segment. The output level of the mapper is xe2x80x985xe2x80x99 if the hsync signal is in a logic level of xe2x80x981xe2x80x99 and the output level of the mapper is xe2x80x98xe2x88x925xe2x80x99 if the hsync signal is in a logic level of xe2x80x980xe2x80x99. Namely, the hsync signal has only the two logic levels, which are continually repeated in every data segment.
FIG. 2 shows a receiving side such as a digital TV receiver in the related art. The receiving side receives a Radio Frequency (RF) signal modulated by a VSB mode through an antenna. A tuner 21 tunes the RF signal to select a frequency of a desired channel and converts the selected frequency into an Intermediate Frequency (IF). A Frequency Phase Locked Loop unit (FPLL) 22 demodulates the IF signal into base band signals I and Q, and locks both the frequencies and the phases. Specifically, the FPLL 22 is a circuit integrating a frequency tracking loop FLL and a phase locked loop (PLL). Thus, the FPLL unit 22 first locks a frequency and upon locking the frequency, locks a phase.
The Q signal is used for the recovery of a carrier in the FPLL 22 while an analog-to-digital (A/D) converter 23 converts the I signal from the FPLL 22 into a digital signal of fixed bits (for example 10 bits). Using the digital signal of fixed bits, the sync signal recovery unit 24 recovers the hsync signal and the field synchronizing signal inserted by the transmission side. The synchronizing signals are used in a timing recovery and an equalization.
Particularly, the synchronizing signals are output to an equalizer/ECC 26. The hsync signal and the field synchronizing signal may be interfered by linear distortion of amplitude and ghost resulting from signal reflections off of structures such as buildings and mountains. Accordingly, the equalizer/ECC 26 conducts an equalization utilizing the restored hsync signal and the field synchronizing signals as training signals to correct interferences to the data, and conducts ECC to correct any errors caused during the transmission through the transmission channel. A video decoder 27 then decodes the equalized and error corrected signal utilizing a Moving Picture Expert Group (MPEG) algorithm and the decoded signals are displayed to the viewers.
Moreover, data is transmitted according to an Advanced Television Systems Committee (ATSC) VSB transmission system proposed in a U.S. digital TV. At the receiving side, as shown in FIG. 2, a same clock as was used in the transmitting side should be generated to recover the transmitted data. This timing recovery is generated by implementing a timing recovery unit 25. Under the current proposed ATSC standard, the timing recovery is implemented by using the hsync signals inserted by the transmitting side.
FIG. 3 is a block diagram of a timing recovery device of a digital TV in the related art. As shown, the timing recovery unit 25 includes a timing error detector 31 which extracts the timing error information from the digital signal output by the A/D converter 23; a loop filter 32 which filters only a low frequency signal component of the timing error information; and a voltage controlled oscillator (VCO) 35 which converts an output frequency in accordance with the low frequency signal component of the timing error information to adjust the sampling timing of the A/D converter 23. In this case, the timing error detector 31 receives a control signal from the synchronizing recovery unit 24 to determine a section of the digital signal for performing a timing recovery. Particularly, FIG. 4 shows a block diagram of a hsync signal recovery unit 24 as disclosed in a co-pending application Ser. No. 09/131,387 entitled xe2x80x9cSignal Recovery System,xe2x80x9d which is fully incorporated herein.
As shown in FIG. 4, the signal recovery unit 24 includes a correlating detector 41 which determines a correlation relation of the digital signal output by the A/D converter 23 with a known hsync signal pattern, i.e. searches for successive groups of the four symbols of the hsync signal within the digital signal; an integrator 42 which adds the data output by the correlating detector 41 for a period of 832 symbols to distinguish the hsync signal section from the data section; a slicer 43 which compares the output value of the integrator 42 with a first predetermined threshold value and outputs a signal indicating the hsync signal section if the output value is over the first predetermined threshold value; and a confidence counter 44 which checks the reliability of the hsync signal section output by the slicer 43 and outputs the control signal indicating a recovery of the hsync signal and the recovered hsync signal if the checked reliability is above a second predetermined value.
Accordingly, the timing error detector 31 of the timing recovery unit 25 extracts the timing error information from the digital signal output by the A/D converter 31 and determines the section of the digital signal for operation, i.e. the hsync signal section, using the control signal from the sync signal recovery unit 24. Thus, upon a recovery of the hsync signal by the sync signal recovery unit 24, the timing error detector 31 initiates the detection of the timing error information within the detected hsync signal section.
The loop filter 32 then filters only the low frequency signal component of the timing error information extracted by the timing error detector 31 using the control signal, to thereby output the filtered signal to the VCO 35. The VCO 35 converts the output frequency in accordance with the low frequency signal component of the timing error information and adjusts the sampling timing, i.e. the A/D clock of the A/D converter 23. The A/D converter 23 is synchronized to the recovered A/D clock and converts the analog signal into the digital signal according to the A/D clock. Thus, the timing recovery unit 25 serves to recover the timing to be used as an A/D clock of the A/D converter 23 using the hsync signal detected by the sync signal recovery unit 24.
Generally, the sync signal recovery unit 24 may lose the once recovered hsync signal due to noise or because the received signal may not be fully synchronous to the A/D clock generated in the receiver. Because the timing recovered by the timing recovery unit 25 is used to adjust the A/D clock, the system would be more efficient if the timing recovery unit 25 stops operating when the hsync signal section is erroneously detected.
However, in the above system, the timing recovery unit 25 may continue to perform timing recovery, regardless of whether the hsync signal section is erroneously detected. For example, the reliability of a correctly recovered hsync signal may be stacked and have well passed the second predetermined value. As a result, even if the once recovered hsync signal is lost, thereby reducing the reliability of the confidence counter 44, the sync signal recovery unit 24 would continue to output the control signal indicating a recovery of the hsync signal until the reliability falls below the predetermined value. Accordingly, the timing recovery unit 25 would continue to perform timing recovery utilizing an erroneously recovered hsync signal.
Moreover, the hsync signal section may slip by, for example, 1 symbol when the received signal is not fully synchronous to the A/D clock generated by the timing recovery unit 25. In such case, the sync signal recovery unit 24 may also continue to output the control signal indicating a recovery of the hsync signal and the timing recovery unit 25 would perform timing recovery on the position where the hsync signal is slipped by 1 symbol, until the reliability falls below the predetermined value. Once the hsync signal is re-recovered, the timing recovery is re-initiated and performed from scratch without regard to the previously generated clock, even when the hsync signal section has been slipped by a few symbols.
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide an efficient timing recovery device in a digital TV to improve the performance of a digital TV receiver.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a timing recovery device in a digital TV includes a sync signal recovery unit which obtains a correlation value of an input signal with a known hsync signal, integrates the obtained value during a predetermined time, compares the integrated value with a predetermined threshold value, and outputs a control signal indicating a recovery of the hsync signal if the recovered hsync signal section has a minimum reliability; and a timing recovery unit controlled by the correlation value and the control signal from the hsync signal recovery unit to perform timing recovery.